Workshop Scope and Goals
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The development of ever larger and more energy-efficient computer systems in recent years has led to more and more systems with heterogeneous computing units (CPUs, GPUs or FPGAS) and systems with heterogeneous storage systems (High Memory Bandwidth). With the rise of persistent memory, attached to the PCIe bus or to the memory DIMMs, the border between storage and memory becomes more and more fluid. Other systems offer different types of compute nodes, so that a group of nodes build the accelerator (modular supercomputing). Hierarchical storage architectures, for example using burst buffers, try to overcome the IO problems. Programming such a system can be a real challenge along with locality, scheduling, load balancing, concurrency and so on.

This workshop focuses on understanding the implications of accelerators and heterogeneous designs on the hardware systems, porting applications, performing compiler optimizations, and developing programming environments for current and emerging systems. It seeks to ground accelerator research through studies of application kernels or whole applications on such systems, as well as tools and libraries and runtime systems that improve the performance and productivity of applications on these systems.

The goal of this workshop is to bring together researchers and practitioners who are involved in application studies for accelerators and other heterogeneous systems, to learn the opportunities and challenges in future design trends for HPC applications and systems.

Topics of interest for workshop submissions include (but are not limited to):

* Strategies for programming heterogeneous systems using high-level models such as OpenMP, OpenACC, low-level models such as OpenCL, CUDA;
* Methods and tools to tackle challenges in scientific computing at extreme scale;
* Strategies for application behavior characterization and performance optimization for accelerators;
* Techniques for optimizing kernels for execution on GPGPU, Intel® Xeon Phi™, and future heterogeneous platforms;
* Models of application performance on heterogeneous and accelerated HPC systems;
* Compiler Optimizations and tuning heterogeneous systems including parallelization, loop transformation, locality optimizations, Vectorization;
* Implications of workload characterization in heterogeneous and accelerated architecture design;
* Benchmarking and performance evaluation for accelerators;
* Tools and techniques to address both performance and correctness to assist application development for accelerators and heterogeneous processors;
* System software techniques to abstract application domain-specific functionalities for accelerators;

Important Dates (AoE)
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Paper Submission: Feb. 08, 2019 (AoE)
Paper Notification: Feb. 27, 2019 (AoE)


Proceedings
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The proceedings of this workshop will be published electronically together with IPDPS proceedings via the IEEE Xplore Digital Library.

Papers Submission Guidelines
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Papers should present original research and should provide sufficient background material to make them accessible to the broader community.

Submitted manuscripts may not exceed 10 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references. See the style templates for latex or word for details.

Submissions will be judged based on relevance, significance, originality, correctness and clarity.

Submission site: https://easychair.org/conferences/?conf=ashes19

Journal Special Issue
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The best papers of AsHES 2019 will be invited to a Special Issue on
Topics on Heterogeneous Computing of the Elsevier International Journal
on Parallel Computing (PARCO).

Steering Committee
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Pavan Balaji, Argonne National Laboratory, USA
Yunquan Zhang, Chinese Academy of Sciences, China
Satoshi Matsuoka, Tokyo Institute of Technology, Japan
Jiayuan Meng, Argonne National Laboratory, USA
Xiaosong Ma, Qatar Computing Research Institute, Qatar
Barbara Chapman, Stony Brook University, USA
Guang R. Gao, University of Delaware, USA
Xinmin Tian, Intel, USA
Michael Wong, Codeplay, UK
James Dinan, Intel Corporation
Sunita Chandrasekaran, University of Delaware, USA

General Chair
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Antonio J. Peña, Barcelona Supercomputing Center, Spain

Program Co-Chairs
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Min Si, Argonne National Laboratory, USA
Lena Oden, FernUni Hagen, Germany

Program Committee
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Ashwin Aji, AMD, USA
James Beyer, NVIDIA Corporation, USA
Sridutt Bhalachandra, Argonne National Laboratory, USA
Adrián Castelló, Universitat Jaume I, Spain
Huimin Cui, Institute of Computing Technology, CAS, China
Khaled Hamidouche, AMD, USA
Jeff Hammond, Intel Corporation, USA
Andreas Herten, Juelich Supercomputing Center, Forschungszentrum Juelich, Germany
Kaixi Hou, NVIDIA Corporation, USA
Gabriele Jost, NASA Ames Research Center/Supersmith, USA
Guido Juckeland, Helmholtz-Zentrum Dresden-Rossendorf (HZDR), Germany
Seyong Lee, Oak Ridge National Laboratory, USA
John Leidel, Texas Tech University, USA
Piotr Luszczek, University of Tennessee, USA
Naoya Maruyama, Lawrence Livermore National Laboratory, USA
Stephen Olivier, Sandia National Laboratories, USA
Guray Ozen, Nvidia/PGI, Germany
Barry L. Rountree, Lawrence Livermore National Laboratory, USA
Bronis R. de Supinski, Lawrence Livermore National Laboratory, USA
Xiaonan Tian, NVIDIA Corporation, USA
Pedro Valero-Lara, Barcelona Supercomputing Center, Spain

Questions?
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Please send any queries about the AsHES workshop to ashes@mcs.anl.gov