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2nd Workshop on SoC Architecture, Accelerators and Workloads (SAW-2)

Feb 12th 2011, San Antonio, Texas, USA
Held in conjunction with HPCA-17

http://hpca17.ac.upc.edu/saw-2/

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Organizing Chairs:
Ravi Iyer Intel Labs ravishankar.iyer@intel.com
Ramesh Illikkal Intel Labs ramesh.g.illikkal@intel.com
Raj Yavatkar Intel raj.yavatkar@intel.com

Overview
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Computing platforms are getting smaller (e.g. handheld devices), richer
(e.g. visual computing applications) and broader (i.e. reaching the masses
via smartphones and other embedded devices). This trend is made possible by
System-on-Chip (SoC) architectures that combine high performance, ultra-low
power general-purpose cores along with a wide spectrum of domain-specific
accelerators or Intellectual Property (IP) blocks. With the recent
introduction of general-purpose compute cores such as Intel(r) Atom(tm)
processor, these platforms have the potential to run a much broader range of
applications than ever before. The goal of this workshop is to bring
together academic researchers and industry practitioners to discuss future
SoC architectures, accelerators and workloads. The research challenges in
SoC platforms are multi-fold, including: (a) providing rich functionality
and high performance while maintaining ultra-low power, (b) attempting to
cover a broad range of applications that can be migrated from mainstream
platforms to SoC devices, (c) enabling a modular architecture and design
environment that improves time-to-market and (d) providing a rich software
programming environment that eases the challenge of developing applications
on a heterogeneous architecture consisting of general-purpose cores as well
as specialized accelerators.

Below is the proposed list of topics for the workshop. Topics include, but are
not restricted to, the following:

* Novel SoC Architectures
- Ultra-Low Power Core Microarchitectures
- Heterogeneous Architectures and Multi-core SoCs
- Fabrics / Network-on-chip
- Cache/Memory Hierarchies
- HW Support for Programmability and Modularity
- Automated Design Environments
- Simulation / Emulation Methodologies
* Emerging Workloads
- New Workloads (e.g. Visual computing examples such as Augmented Reality, Multi-modal interfaces, etc)
- Workload Analysis for optimization and acceleration
- Workload Partitioning between Cores and Accelerators
- Performance Monitoring and Evaluation
- Case Studies of SoC applications
* Novel Accelerator Designs
- Specialized Accelerator Architectures and Designs
- Domain-Specific Programmable/Configurable Accelerators
- Accelerator Interfaces for Programmability
- Development Environments for Accelerator Design
- System-Level integration of Accelerators
* SoC Systems Software
- Modular Systems Software
- Heterogeneous Programming Languages and Environments
- Application Development Environments
- Runtime Libraries and Environments

Submission Guidelines:
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Interested authors are encouraged to submit extended abstracts (1 - 2 pages)
or short papers (6 pages) by email to the organizing chairs (Ravi Iyer,
Ramesh Illikkal and Raj Yavatkar). The deadline for submission is Nov 19th
(by midnight in US PST zone). Final (short) papers will be due on Jan 10th
2011 and will be printed in a workshop proceedings made available to the
workshop attendees.

Note: Best papers from SAW-2 will be also considered for subsequent
publication in IEEE Computer Architecture Letters. More information on this
will be available later.

Important Dates:
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Abstract / Paper Submission Nov 19th 2010
Author Notification Dec 20th 2010
Final Paper Submission Jan 10th 2011
Workshop Feb 12th 2011