Since 2011, the most powerful supercomputers systems ranked in the Top500 list are hybrid systems composed of thousands of nodes that includes CPUs and accelerators, as Xeon Phi and GPUs. Programming and deploying applications on those systems is still a challenging work, due to the complexity of the system and the need to mix several programming interfaces (MPI, CUDA, Intel Xeon Phi) in the same application.
This Workshop is aimed to explore the state of the art of developing applications in accelerated massive HPC architectures, including practical issues of hybrid usage models with MPI, OpenMP, and other accelerators programming models. The idea is to publish novel work on the use of available programming interfaces (MPI, CUDA, Intel Xeon Phi) and tools for code development, application performance optimizations, application deployment on accelerated systems, as well as the advantages and limitations of accelerated HPC systems. Experiences with real-world applications, including scientific computing, numerical simulations, healthcare, energy, data-analysis, etc. are also encouraged.
Submission Guidelines

Contributors are invited to submit a full paper as a PDF document not exceeding 6 pages in English. The title page should contain an abstract of at most 100 words and five specific, topical keywords. The paper must be formatted according to double-column ACM ICPS proceedings style. The usage of LaTeX for preparation of the contribution as well as the submission in camera ready format is strongly recommended. Style files can be found at www.acm.org/publications/icps-instructions/.
All contributions will be fully peer reviewed by the program committee. Registration for EuroMPI/USA 2017 main conference is mandatory to attend workshops.
The paper submission online system is open: https://www.easychair.org/conferences/?conf=esaa2017.
List of Topics

Tools, libraries, and environments for accelerators.
Hybrid and heterogeneous programming with MPI and accelerators.
Performance evaluation scientific applications based on accelerators.
Automatic performance tuning of scientific applications with accelerators.
Integrating accelerators on existing HPC middlewares.
Run-times for accelerators.
Energy efficient HPC solutions based on accelerators.
Storage cache solutions based on SSD accelerators.
Parallel data analysis for MPI and SSD.
Real-world scientific and engineering applications using accelerated HPC.
Future trends and prospects for accelerated HPC.
Committees

Program Committee

Prof. Jesus Carretero. University Carlos III of Madrid, Spain
Dr. Javier Garcia Blas. University Carlos III of Madrid, Spain
Organizing committee

Ivona Brandic. Vienna University of Technology, Austria
Minyi Guo, Shanghai Jiao Tong University, China
Francisco Igual Peña, Universidad Complutense, Spain
Florin Isaila, Argonne National Labs, Chicago, USA
Emmanuel Jeannot, INRIA, France
Hai Jin, Huazhong University of Science and Technology, China
Timothy K. Jones, University of Cambridge, UK
Christos Kartsaklis, Oak Ridge National Laboratory, USA
Laurent Lefevre, INRIA, Ecole Normale Superieure of Lyon, University of Lyon, France
Diego R. Llanos, University of Valladolid,Spain
Dimitar Lukarski, Uppsala University, Sweden
Svetozar Margenov, Bulgarian Academy of Sciences, Bulgaria
Raffaele Montella, University of Napoli Parthenope, Italy
Ravi S Nanjundiah, Indian Institute of Science in Bangalore, India
Ariel Olesiak, Poznan Supercomputing and Networking Center, Poland
Antonio J. Peña, Argonne National Labs, Chicago, USA
Enrique S. Quintana-Orti, Universidad Jaume I de Castellon, Spain
Matei Ripeanu, University of British Columbia, Canada
Leonel Sousa, Instituto Superior Tecnico, Universidade de Lisboa, Portugal
Alexander Supalov, INTEL, USA
Rupa K. Thulasiram, University of Manitoba, Canada
Manuel Ujaldon, Universidad de Malaga, Spain
Roman Wyrzykowski, Czestochowa University of Technology, Poland
Julius Zilinskas, Vilnius University, Lithuani
Xingshe Zhou, Northwestern Polytech University, China