ISQED'25 Conference Information

AI/ML & Electronic Design, Security, IoT, Autonomous Vehicles, Quantum Computing

The 26th International Symposium on Quality Electronic Design (ISQED'25) stands as the leading conference at the intersection of multiple disciplines within electronic design. It serves as a crucial link between various stakeholders in the Electronic/Semiconductor ecosystem, including providers of electronic design tools, integrated circuit technologies, semiconductor technology, and those involved in packaging, assembly, and testing. The goal is to foster a comprehensive approach to achieving excellence in design quality. ISQED has consistently enjoyed the technical backing of esteemed organizations such as IEEE CASS and IEEE EDS, and has collaborated with ACM/SigDA. All past conference proceedings and papers have been documented and made available through the IEEE Xplore digital library, with indexing provided by Scopus.

Conference Venue
ISQED'25 conference will be held in Seven Hills Conference Center, located in San Francisco State University, 800 Font Blvd, San Francisco, CA 94132.

If you are using navigator the address to use is: 796 state drive, San Francisco, CA 94132 (Note: use Google Map App instead of Apple Map App). At the end of State Drive is the Public Parking Lot (“Lot 20”). Parking is $6.25 for less than 2 hours, and $10 for 2+ hours. Pay stations on each floor accept $1, $5 and $10 bills as well as credit/debit cards. Be advised, pay stations do not provide change. Please have exact amount. From the garage, Seven Hills' entrance can be accessed from State Drive by walking Southwest towards the A.S. Children’s Center and taking the staircase beside it up one flight. Wheelchair access: go past the A.S. Children’s Center and take a left onto the path. Follow to the entrance to the Seven Hills Conference Center. Also, please check the Driving Direction file.

If you are looking for hotel accommodation near university please visit this link: Off-Campus Housing Options


26th International Symposium on Quality Electronic Design (ISQED'25)

For any question please contact the publication committee by sending email to isqedisqed@gmail.com. Note the following important dates:

IMPORTANT DATES (Midnight, US Pacific Time)
FINAL Paper Submission Deadline
Nov. 17, 2024
Acceptance Notification Jan. 15. 2025
Camera-Ready Paper Due Feb 17, 2025
Presentation Video, and Speaker Bio March 25, 2025


Papers are requested in the following areas
A pioneer and leading multidisciplinary conference, ISQED accepts and promotes papers related to the manufacturing, design and EDA. Authors are invited to submit papers in the various disciplines of high level design, circuit design (digital, analog, mixed-signal, RF), test & verification, design automation tools; processes; flows, device modeling, semiconductor technology, advance packaging, and biomedical & bioelectronic devices. All past Conference proceedings & Papers have been published in IEEE Xplore digital library and indexed by Scopus.

The details of various topics of paper submission are as follows:

Hardware and System Security (HSS)
Attacks and countermeasures including but not limited to side-channel attacks, reverse engineering, tampering, and Trojans
Hardware-based security primitives including PUFs, TRNGs and ciphers
Security, privacy, trust protocols, and trusted information flow
Ensuring trust using untrusted tools, IP, models and manufacturing
Secure hardware architectures Secure memory systems
Post-quantum security primitives
Security challenges and opportunities of emerging nanoscale devices
IoT and cyber-physical system security
Any other topics related to hardware security
Electronic Design Automation Tools and Methodologies (EDA)
EDA and physical design tools, processes, methodologies, and flows
Design tools for analysis/ tolerance of variation, aging, and soft-errors
Design and maintenance of hard and soft IP blocks
Challenges and solutions of integrating, testing, qualifying and manufacturing IP blocks from multiple vendors
EDA for non-traditional problems such as smart power grid and solar energy
EDA tools and methodologies for 3D integrations, and advanced packaging
Modeling and Simulation of Semiconductor Processes and Devices (TCAD)
CAD for bio-inspired and neuromorphic systems
EDA tools, methodologies and applications for Photonics devices, circuit and system design
EDA for MEMS Any other topics related design automation tools and methodologies
Design Test and Verification (DTV)
Hardware and software formal-, assertion-, and simulation-based design verification techniques
All areas of DFT, ATE and BIST for digital designs, analog/mixed-signal IC's, SoC's, and memories
Test synthesis and synthesis for testability
Fault diagnosis, IDDQ test, novel test methods, effectiveness of test methods, fault models and ATPG, and DPPM prediction
SoC/IP testing strategies Design methodologies dealing with the link between testability and manufacturing
Hardware/software co-verification
Advanced methodologies, testbenches, and flows (e.g., UVM, HDLs, HVLs)
Formal and semi-formal verification and validation techniques
Safety and security in verification and validation New methods and tools supporting functional safety and security
Self-checking testbenches in analog verification
Any other topics related to design test and verification
Emerging Device and Process Technologies and Applications (EDPT)
Design, simulation and modeling of emerging technologies
Design, simulation and modeling of emerging non-volatile memory and logic, such as STT-RAM, PC-RAM, R-RAM, and Memristors
Application of emerging devices for storage and computation including but not limited to cognitive, neuromorphic, or quantum computing
Qubit technologies and quantum computing Specialty technologies such as MEMs, NEMs
Novel or emerging solid state nanoelectronic devices and concepts
Design and Technology Co-Optimization
Optimization-based methodologies that address the interaction between design (custom, semi-custom, ASIC, FPGA, RF, memory, etc.)
Advanced-node manufacturing techniques such as multiple patterning, EUV lithography, DSA lithography,
Advanced interconnect (e.g., air gap for local interconnect, Si photonics, etc.).
Modeling, analysis, and optimization of technology implications on performance metrics like power consumption, timing, area, and cost.
Design methods and tools to improve yield and manufacturability.
Any other topics related to emerging device technologies and applications
Circuit Design, 3D Integration and Advanced Packaging (ICAP)
Low power, high-performance, and robust design of logic, memory, analog, interconnect, RF, programmable logic, and FPGA circuits
Techniques for leakage control, power optimization, and power management
Analog circuit design including but not limited to all-digital PLLs and DLLs, ADC's and DAC's
Adaptive and resilient digital circuits and systems
On-chip process, voltage, temperature, and aging sensors and monitoring
Hardware design for IoT sensors and actuators including digital logic, memory design, wireless communications, energy harvesting, signal processing, and power management
Innovative packaging technologies including 3D IC, 2.5D or interposer, and multi-chip module and their impact on system design
Design techniques, methodologies and flows for vertically integrated circuits/chips
Modeling and mitigation of device interactions for 3D ICs
Design of die-to-die interfaces in 3D/2.5D ICs
Design-for-testability and system-level design issues in 3D/2.5D
Die-package co-design
Any other topics related to circuit design, 3D integration and advanced packaging
System-level Design and Methodologies (SDM)
Methods and tools aiming at quality of systems including multi-core processors, graphics processors embedded systems, SoC, novel accelerator designs, and heterogeneous architecture designs
System-level trade-off analysis and multi-objective (e.g. yield, power, delay, area, etc.) optimization
System level power and thermal management
Exploration of influence of emerging technologies on the system level design
System level modeling and simulation to characterize effects of process, voltage, temperature, and aging on power, performance, and reliability
Cyber-Physical Systems – Design, Methodologies & Tools
HW/SW co-design, co-simulation, co-optimization, and co-exploration
HW/SW prototyping and emulation on FPGAs
Micro-architectural transformation
System communication architecture
Application driven heterogeneous computing platforms
Network-on-chip design methodologies
Any other topics related to system level design and methodologies
Cognitive Computing Hardware (CCH)
Neuromorphic computing and non-Von Neumann architectures
Hardware and architecture for neural networks and system-level design for (deep) neural computing Neural network acceleration techniques including GPGPU, FPGA and dedicated ASICs
Safe and secure machine learning Hardware accelerators for Artificial Intelligence Cognitive-inspired computing fundamentals
Cognitive-inspired computing systems
Cognitive-inspired computing with big data
Cognitive-inspired intelligent interaction AI-assisted cognitive computing approaches
Brain analysis for cognitive-inspired computing Internet of cognitive Things
Cognitive environment, sensing and data
Cognitive robots and agents Security issue in cognitive-inspired computing
Test-bed, prototype implementation and applications
Any other topics related to cognitive computing hardware

Submission of Papers
Paper submission must be done on-line through the conference web site: www.isqed.org. The guidelines for the final paper format are provided on the conference web site. Authors should submit original, unpublished papers along with an abstract of about 200 words. The manuscripts should be at least four (4) pages long but not exceed eight (8) pages, should not use smaller than 10pt font size, and must be consistent with the format provided in the conference website: www.isqed. org. The manuscripts longer than 10 pages and/or written in less than 10-pt font sizes will not be reviewed. To permit a blind review, do not include name(s) or affiliation(s) of the author(s) on the manuscript and abstract. The complete contact author information needs to be entered separately.
The manuscripts identifying the name and/or affiliations of the authors in the submitted manuscript will be rejected without review. Please check the as-printed appearance of your paper before sending your paper. In case of any problems email isqedisqed@gmail.com.

See the MS Word template at the bottom of this page. Use the on-line paper submission procedure by clicking the following link: ON-LINE. If you have problem accessing the paper submission site it is located at: https://softconf.com/n/isqed2025



ISQED 2025 Special Issue Journals & Selection Process
Selected papers from ISQED 2025 will be invited for submission to special issues of JLPEA. The selection process for these special issues will take place after the conference is completed and will be based on reviewer feedback and the quality of the conference presentation.


Work in Progress (WIP) Submission
Ongoing research projects can be presented at ISQED under the Work in Progress (WIP) category. This provides a unique opportunity to authors to receive early feedback on their current work. For more information please click HERE.


Workshop/Tutorial Proposals
Several workshop/tutorial sessions will be held on the first day, and would offer valuable opportunities for practicing professionals to refresh or upgrade their skills in quality-based IC design techniques, methodologies and tools. These sessions are intended to supplement the conference by providing in depth, practical and proven design solutions. Workshops/Tutorials will be taught by experts in the field, who are intimately involved with the issues and solutions in their perspective areas, from both industry and academia. If interested in offering a tutorial, please send your tutorial proposals to the ISQED workshop/tutorial committee to isqedisqed@gmail.com

The proposal should include:

Title of Workshop/Tutorial
Name of organizer
Name(s), address, and affiliation of the Moderator
Name(s), address, and affiliation of presenter(s)
Half-page summary of each presenter's biography
You may send your proposal by email as text or as an Adobe PDF file. The presentations must be technical, up to date, relevant, and target the design community. Marketing presentations will not be accepted. In order to meet the conference timeline, we would like to have your proposal no later than Nov. 22, 2024. Please check the archive section of the web site for a listing of past tutorials.

Templates and Resouces for Authors & Speakers
Paper Submission Site
IEEE Manuscript Templates for Conference Proceedings
Oral Session Preparation & Presentation Guidelines
Poster Session Preparation & Presentation Guidelines
Workshop/Tutorial Guidelines