NANOARCH is the annual cross-disciplinary forum for the discussion of novel post-CMOS nanocomputing directions and emerging nanoscale CMOS. The symposium seeks papers on innovative ideas for solutions to the principal challenge facing integrated electronics in the 21st century - how to design, fabricate, and integrate nanosystems to overcome the fundamental limitations of CMOS. In particular, such systems could (1) contain unconventional nanodevices with unique capabilities, including directions beyond simple switches, (2) introduce new logic and memory concepts, (3) involve novel circuit styles, (4) introduce new concepts for computing, (5) reconfigure and/or mask faults at much higher rates than in CMOS, (6) involve new paradigms for manufacturing, and (7) rethink the methodologies and design tools involved.

This symposium includes several exciting sessions and opportunities for interaction. In addition to Regular papers presenting original techniques / directions, it invites the community to also submit Nanofabric Progress Updates giving a progress update of their nanofabrics directions to date across devices, circuits, architecture and manufacturability aspects - e.g. 2D/3D nanowire, magnonic, memristor, CNT, graphene, FinFETs, and QCA based directions.

In addition, Crosscut papers are invited from the broader nanotechnology community to highlight promising nanomaterial, nanodevice, nanomanufacturing, and integration ideas with application potential in nanoscale architectures.

Example topics (both theoretical and experimental) of interest include (but are not limited to):

Novel nanodevices and manufacturing/integration ideas with a focus on nanoarchitectures
Nanoelectronic circuits, nanofabrics, computing paradigms and nanoarchitectures
2D/3D/hybrid nanodevice integration and manufacturing, with variability, defect and fault tolerance
Nanodevice and nanocircuit models, methodologies and computer aided design tools
Fundamental limits of computing at the nanoscale