Issues related to verification and security are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in quality, reliability and security needs in several application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective verification techniques and security solutions. These needs have increased dramatically with the increased complexity of complex electronic systems and the fast adoption of these systems in all aspects of our daily lives. The goal of IVSW is to bring industry practitioners and researchers from the fields of verification, validation, test, reliability and security to exchange innovative ideas and to develop new methodologies for solving the difficult challenges facing us today in various SOC design environments. IVSW 2017 is sponsored by IEEE Council on Electronic Design Automation (CEDA).

The topics of interest include (but are not limited to) the following ones:
• Verification challenges of IoT
• High-level test generation for functional verification
• Emulation techniques and FPGA prototyping
• Triage and debug methodologies
• Silicon debugging
• Low-power verification
• Formal techniques and their applications
• Verification coverage
• Performance validation and characterization
• Design for Verifiability (DFV)
• Memory and coherency verification
• ESL design and Virtual Platforms
• Security verification
• Design for security
• Hardware Security IP
• Secure circuit design
• Fault-based attacks and counter measures
• Security solutions for analog/mixed signal circuits
• Security Applications in automotive, railway, avionics and space
• Internet of Things (IoT) security considerations
• Data analytics in verification and security
• Security EDA tools
• Hardware/software security and verification

Author’s Information: Authors are invited to submit papers or abstracts in the above technical areas. All submissions must be done electronically following the instructions at the workshop web site. IVSW formal Proceedings will get published by IEEE Xplore after the workshop. Inclusions in the formal proceedings is optional. There is a 6 page limit for each paper. Additional pages can be included for a fee. Papers should be in the standard IEEE conferences double-column format. At least one author of each accepted paper must attend and register for the workshop to present the paper.

Special Sessions, Panels and Tutorials: Proposals for special sessions, panels and tutorials are also invited. Please submit the abstract of your proposal electronically as early as possible before the deadline.

Key Dates:
Submission deadline: February 28, 2017 – Notification of acceptance: April 6, 2017 – Camera-ready papers due: May 7, 2017

Federative Event on Design for Robustness (FEDfRo): IVSW’17 is held as part of the 2nd Federative Event on Design for Robustness (FEDfRo). IVSW will be co-located with two successful test related conferences: the Int’l On-line Test Symposium (IOLTS) and the Int’l Mixed Signal Test Workshop (IMSTW). This will be an ideal environment for cross- examination of test, verification, reliability and security experiences and innovative solutions. Registered attendees of any of the three events will be allowed to attend the technical sessions of the other two events. The plenary session and social activities of the three events will be done jointly. For all details about this federated event see: http://tima.imag.fr/conferences/fedfro/fedfro17/

About the Location:
IVSW 2017 will be held at Thessaloniki, Greece. The hotel faces the beautiful seafront and the area has many attractions including the White Tower, the beautiful Bay of Thermaikos, famous archeological sites, and several interesting museums.

Questions:
Contact IVSW 2017 General Chair: Magdy Abadir;  magdy.abadir@gmail.com