THE 44TH IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD 2026) 
NOVEMBER 16-18, 2026, HONG KONG 
https://www.iccd-conf.com 

ABOUT IEEE ICCD 
ICCD encompasses a wide range of topics in the research, design, and implementation of computer systems and their components. The multi-disciplinary emphasis of ICCD provides an ideal environment for developers and researchers to discuss practical and theoretical work covering systems and applications, computer architecture, verification and test, design tools and methodologies, circuit design, and technology. 

IMPORTANT DATES 
Abstract Registration: June 03, 2026 23:59 AOE (strict final deadline)
Full Paper Submission: June 10, 2026 23:59 AOE (strict final deadline)
Notification: August 20, 2026 
Camera-Ready Paper: September 17, 2026 

SUBMISSION INFORMATION 
Papers must be formatted according to the IEEE conference paper guidelines using the letter page size and a 10-point font size. 
Submissions must be double-blind. All author identifying information must be removed. 
Initial submissions are limited to 8 pages including references and appendices. ICCD reserves the right to accept a submission as a short 4-page paper. 
Each accepted paper requires a unique full registration and an in-person presentation to be included in the program and the published proceedings. 

TECHNICAL TRACKS AND TOPICS 
1.     Computing Systems: System architecture; Software-hardware co-design; System support for multi/many cores, co-processors/accelerators; System support for speed, security, reliability, and energy efficiency and proportionality; Virtual memory; System support for emerging technologies; Storage systems for data centers and cloud/edge computing, high-performance computing (HPC), exascale systems, and serverless computing. 
2.     Software Architectures, Compilers, and Tool Chains: Software architectures, compilers, programming language/model, firmware, OS, hypervisor, runtime design, and co-design for embedded/real-time systems; Middleware for computing systems, including resource-awareness, reconfiguration, energy/power management, task scheduling; Compiler support for enhanced debugging, profiling, and traceability; Processor modelling, optimization and simulation. 
3.     Hardware Architectures: Design for high-performance, low-power, secure, and reliable processor microarchitectures; Hardware acceleration for computing-intensive/data-intensive applications, such as machine learning, autonomous driving, robotics, quantum, neuromorphic, bio-inspired, and so forth; In-memory/near-memory computing architectures; Hardware design with emerging technologies, including emerging memory, photonics, and so forth. 
4.     Test, Verification, and Security: Design error debug and diagnosis; Fault modelling; Fault simulation and ATPG; Analog/RF testing; Statistical test methods; Large volume yield analysis and learning; Fault tolerance; DFT and BIST; Functional, transaction-level, Register Transfer Level (RTL), and gate-level modelling and verification of hardware designs; Equivalence checking, property checking, and theorem proving; Constrained-random test generation; High-level design and System on Chip (SoC) validation; Hardware security primitives and methodologies; Side-channel analysis, attacks and mitigations for processors and accelerators; Interaction between test, security and trust. 
5.     Electronic Design Automation: System-level design and synthesis; High-level, logic, and physical synthesis; Analysis and optimization of timing, power, variability/yield, temperature, and noise; Physical design, including partitioning, floor-planning, placement, routing, and clock tree synthesis; Tools for multiple-clock domains, asynchronous, and mixed-timing methodologies; CAD support for accelerators, FPGAs, SoCs, ASICs, NoC, and general-purpose processors; CAD for manufacturing, test, verification, and security; Tools and design methods for emerging technologies (photonics, MEMS, spintronics, nano, quantum); Interaction of Electronic Design Automation (EDA) and AI/ML. 
6.     Logic and Circuit Design: Circuit design techniques for digital, memory, analog, and mixed-signal systems; High-performance and low-power circuit techniques; Robust circuit design under process variability, noise, radiation, and reliability constraints; Emerging and maturing device and circuit technologies, including MEMS, nano-spintronics, flexible electronics, in-memory computing, and quantum devices; Asynchronous circuit design; Signal-processing, datapath, and control circuits, including quantum circuit optimization, qubit control and readout electronics, and circuit-level error mitigation techniques. 

ORGANIZING COMMITTEE 
General Chairs: Wei Zhang, HKUST; Jiang Xu, HKUST (GZ) 
Program Chairs: Weichen Liu, NTU Singapore; Yingjie Lao, Tufts University 
Special Session Chairs: Jiayi Huang, HKUST (GZ); He Li, Southeast University 
Student Forum Chairs: Zhe Lin, Sun Yat-Sen University; Xinyu Chen, HKUST (GZ) 
Tutorial Chairs: Ngai Wong, University of Hong Kong; Sharad Sinha, IIT Goa 
Panel Chairs: Fengbin Tu, HKUST; Xuanqi Chen, Huawei Incorporated 
Finance Chair: Ceyu Xu, HKUST 
Publication Chair: Fubing Mao, HUST 
Registration Chair: Nan Guan, City University of Hong Kong 
Web Chairs: Jingyi (Carol) Li, HKUST; Shien Zhu, ETH Zurich 
Publicity Chairs: Huanrui Yang, University of Arizona; Bei Yu, Chinese University of Hong Kong 

STEERING COMMITTEE 
Omer Khan, UConn (Chair) 
Georgi Gaydadjiev, TU Delft 
Kee Sup Kim, Axion, Korea 
Peter-Michael Seidel, University of Hawaii 
Sandip Kundu, UMass Amherst 
 
For any questions about submission, please contact Weichen Liu at liu@ntu.edu.sg.