VISA 2026 examines the virtual ISA — a stable, hardware-agnostic abstraction between high-level programming models and diverse hardware backends — as the pivotal interface of the agentic era: the contract surface where LLM-driven code synthesizers, autonomous autotuners, compilers, and microarchitectural innovation meet. When the programmer is a machine, the ISA must be self-describing enough to reason over and verifiable enough to trust.

The accelerator landscape is undergoing rapid and continuous transformation. However, this rapid architectural evolution introduces a critical fragmentation problem: each accelerator spawns its own toolchain, compiler backend, and software stack, leading to duplicated engineering effort, poor portability, and steep developer learning curves across targets. Virtual ISA enables compiler reuse across heterogeneous targets, rapid hardware prototyping, software longevity across architectural generations, and composable optimization at the right abstraction level.

Despite this progress, the community lacks a dedicated venue for the cross-cutting challenges of Virtual ISA design, compilation, DSL integration, and co-design — the gap this workshop aims to fill.

We invite short papers (4–6 pages, IEEE format) describing work in progress, position papers, vision papers, or early results. The scope spans the full accelerator stack — ISA design and semantics, compilation and optimization, DSLs and programming models, hardware co-design, and deployment experience.

The agent-facing interface is the flagship theme that runs through all of them: wherever your work sits, we encourage you to ask how the problem changes when the primary reader and writer of the ISA is a machine.


TOPICS OF INTEREST

Topics include, but are not limited to:

1. Agent-Facing Virtual ISA Interfaces

- Self-describing virtual ISAs exposing semantics, costs, and resource footprints to LLM reasoners
- Well-typed and verifiable contracts for reliable agent-generated code
- Equivalence checking for machine-generated kernels
- LLM-guided lowering and kernel synthesis
- Closed-loop autotuning through the virtual ISA layer
- Safety and sandboxing for agent-generated kernels
- Benchmarks for the agent-programmability of virtual ISAs
- Self-evolving virtual ISAs and lowering strategies

2. Virtual ISA Design and Abstraction

- Stable virtual ISA boundaries
- Formal semantics and correctness
- Versioning and compatibility strategies
- Capability negotiation, feature discovery, and introspection
- Effect systems, memory models, and concurrency semantics
- Abstractions for heterogeneous architectures

3. Virtual ISA and Architecture Co-design

- Late binding of physical resources during virtual-to-physical lowering
- Cost-model-aware virtual ISAs
- Interfaces for parallelism, dataflow, precision, and locality
- Reconfigurable and spatial architectures
- Emerging hardware features and accelerator architectures
- Dynamic-shape execution under stable semantics
- Programmability–performance tradeoffs
- AI acceleration, LLM serving, MoE, sparsity, processing-in-memory, chiplets, and KV-cache-oriented systems

4. Compiler Optimizations

- Lowering and legalization targeting virtual ISAs
- Optimization across virtual and physical ISA boundaries
- Polyhedral, tile-level, and search-based optimization
- Profile-guided compilation
- Equivalence checking and differential testing
- LLM-aware compilation
- Kernel fusion, scheduling, and graph partitioning
- Directive- and annotation-guided compilation

5. DSLs and Programming Models

- Tile, dataflow, graph, and agentic pipeline languages
- DSL frontends targeting virtual ISAs
- Type systems for accelerator programming
- Autotuning and search-based code generation
- Programming abstractions for emerging AI workloads
- LLM inference and training, MoE routing, long-context attention, KV-cache management, and multimodal or agentic serving
- Profiling APIs and feedback-driven optimization

6. Case Studies and Infrastructure

- Virtual ISA deployments in AI, HPC, networking, and signal processing
- Open-source frameworks and benchmarks
- Simulation, modeling, and hardware/software co-design flows
- Production experience with MLIR dialects, PTX, SPIR-V, StableHLO, TOSA, Triton-IR, CUDA Tile IR, Ascend PTO, and related systems


SUBMISSION GUIDELINES

Paper length:
4–6 pages using the IEEE conference two-column template.

Paper types:
Work-in-progress papers, position papers, vision papers, and early-results papers are welcome.

Reviewing:
The review process is single-blind. Author names and affiliations should appear in the submission.

Submission site:
https://visa2026.hotcrp.com/

The HotCRP site is currently pending activation. Submissions will open after approval.

Publication:
Accepted papers will be presented at the workshop and posted on the VISA 2026 website. The workshop is non-archival, and submission does not preclude later publication at another venue.

Presentation:
At least one author of every accepted paper must register for the workshop through MICRO 2026 and present the work.

Review process:
Every submission will receive at least three reviews. Papers will be evaluated for relevance, originality, soundness, and potential to spark discussion.


IMPORTANT DATES

Paper submission deadline:
September 25, 2026, 23:59 AoE

Author notification:
October 9, 2026, 23:59 AoE

Camera-ready papers:
October 16, 2026, 23:59 AoE

Workshop:
October 31, 2026
13:00–17:00 EET
Athens, Greece


CONTACT AND FURTHER INFORMATION

Workshop website:
https://visaworkshop.github.io/2026/

Call for Papers:
https://visaworkshop.github.io/2026/cfp.html

Contact:
visa.workshop.chairs@gmail.com