The International Symposium on Asynchronous Circuits and Systems (ASYNC) is the premier forum for researchers to present their latest findings in the area of asynchronous design. Asynchronous circuit and architecture design is at the heart of network on chips, neuromorphic designs, and data driven processing pipelines. It is particularly well-suited for distributed tasks in fast and low-energy processing and communication and for tasks that require robustness to environmental variations and noise.

Regular Papers:

Authors are invited to submit papers on any aspect of asynchronous design topics, ranging from design, synthesis, and test, to asynchronous applications in system-level integration and emerging computing technologies. Topics of interest include:

Asynchronous pipelines, architectures, CPUs, and memories
Synchronization, arbitration, and metastability
Asynchronous techniques in mixed-timed circuits, clock domain crossing, and latency-tolerant synchronous design
Asynchronous techniques in multi-chip interconnects, networks-on-chips, GALS systems, and 3D integration
Asynchrony in emerging technologies (bio, neural, nano, and quantum computing)
CAD tools for asynchronous design, synthesis, analysis, and optimization
Formal methods for verification and performance/power analysis
Fault tolerance, variability-tolerant, and resilient design
Asynchronous logic in ultra-low power and power-constrained systems, and mixed-signal/analog design
Case studies, comparisons, and applications of asynchronous circuits

Submissions must report original scientific work relevant to ASYNC in 6-8 pages IEEE conference format (double-column, 10pt or larger) with author information concealed. Authors who feel that extra pages are absolutely required to achieve top quality for their article may contact the Program Chairs. Accepted papers must be presented to be published in the IEEE digital library (IEEE Xplore) and the symposium proceedings.
Industrial Papers:

ASYNC 2026 will include a special session with papers from industry on the state-of-the-art application of asynchronous designs to both existing and emerging technologies. We solicit 1-4 page submissions, using the IEEE two-column conference format. These papers will go through a separate lightweight review process. Accepted papers must be presented to be published in the IEEE digital library (IEEE Xplore) and the symposium proceedings.
Fresh Ideas & CAD Demo Session:

ASYNC 2026 will accommodate a special session to present “fresh ideas” in asynchronous design that are not yet ready for publication, as well as CAD tools to try out live. We solicit 1-2 page extended abstracts submissions, which will go through a separate lightweight review process. Accepted submissions that are presented will be distributed as handouts at the Symposium.