First Workshop on software-controlled, adaptive fault-tolerance in
microprocessors (SCAFT 2011)

http://scaft.in.tum.de

22 February 2011, Lake Como, Italy

Held in conjunction with

ARCS 2011 - Architecture of Computing Systems
http://conferences.dei.polimi.it/arcs2011

IMPORTANT DATES

Extended Abstracts due: 17 December 2010
Author notification: 8 January 2011
SCAFT workshop date: 22 February 2011


OVERVIEW

Future microprocessors will have more transistors, smaller feature sizes,
a higher complexity, lower voltages, and higher clock frequencies
as today. All these factors will increase the probability of design-,
manufacturing-, and operational faults. Therefore, in order to obtain a
satisfying production yield, and in order to fulfill the dependability
requirements of modern applications, fault-tolerance techniques within
digital designs will be of crucial importance. However, simple solutions like
triple modular redundancy (TMR), as they are used in today's safety-critical
application areas, are certainly to expensive for general purpose processors
in data centers and embedded computing.

This workshops therefore addresses light-weight fault tolerance techniques,
which are implemented in hardware, but might be controlled from higher
software layers. In such a way, the application or operating system can decide
which degree of fault-tolerance is required. Thus, the software controls both
the increase in dependability, but also the performance overhead involved.

In particular, the workshop adresses the following topics:

* techniques against different types of faults, such as
+ design, manufacturing, and operational faults
+ permanent, intermittent, and transient faults
+ faults affecting the control unit, arithmetic unit, and memory unit
* light-weight fault masking
* techniques to detect errors, like error detecting codes and checker
circuits
* fault diagnosis and root-cause analysis, online failure prediction
* on-chip backward recovery techniques (e.g. pipeline flush and re-execution)
* forward recovery techniques (notification of higher layers)
* fault-tolerance techniques aware of the environment (temperature,
vibration, age ...)
* software-controlled fault-tolerance
* error detection on the electrical layer
* fault-tolerant caches
* re-using unused parallel resources for fault-tolerance
* fault-tolerance in multi- and manycore processors
* fault-tolerance in systems on a chip
* evaluation of fault-tolerant architectures, both by measurement
and model-based approaches
* fault-injection techniques
* finding a tradeoff between dependability, performance, and power
consumption

SUBMISSION DETAILS

Evaluation is based on a four page extended abstract which has to be submitted
until 17 December 2010 (strict deadline). Accepted abstracts will appear in
the workshop proceedings published by the VDE-Verlag.

The deadline for the full papers is 15 April 2011. There will be a second
round of reviewing for the full papers. Full papers will appear in a special
issue of "Microprocessors and Microsystems", published by Elesevier:

http://www.elsevier.com/wps/find/journaldescription.cws_home/525449/description

Further details on the submission process, including formatting instructions,
can be found on the workshop's webpage at http://scaft.in.tum.de

ORGANIZERS

C. Trinitis, M. Walter, J. Weidendorfer
Lehrstuhl für Rechnertechnik und Rechnerorganisation (Informatik 10)
Technische Universität München, Germany

TECHNICAL PROGRAM COMMITTEE

Fevzi Belli Universität Paderborn, Germany
Mladen Berekovic Technische Universität Braunschweig, Germany
Greg Bronevetsky Lawrence Livermore National Lab, USA
Rainer Buchty Universität Karlsruhe,
Eberhard-Karls-Universität Tübingen, Germany
Masashi Imai University of Tokyo, Japan
Klaus Echtle Universität Duisburg-Essen, Germany
Bernhard Fechner Fernuniversität Hagen, Germany
Elena Gramatova Slovenská technická univerzita v Bratislave, Slovakia
Joshua Hursey Oak Ridge National Laboratory, USA
Jörg Keller Fernuniversität Hagen, Germany
Vyacheslav Kharchenko National Aerospace University, Ukraine
Erik Mähle Universität zu Lübeck, Germany
Miroslaw Malek Humboldt-Universität zu Berlin, Germany
Dimitris Nikolos University of Patras, Greece
Toshi Sato Fukuoka University, Japan
Martin Schulz Lawrence Livermore National Lab, USA
Peter Sobe Hochschule für Technik und Wirtschaft Dresden, Germany
Janusz Sosnowski Politechnika Warszawska, Poland
Carsten Trinitis Technische Universität München, Germany
University of Bedfordshire, UK
Peter Tröger Hasso-Plattner-Institut Potsdam, Germany
Max Walter Technische Universität München, Germany
Josef Weidendorfer Technische Universität München, Germany
Hee Yong Youn Sungkyunkwan University, Korea
Tomohiro Yoneda National Institute of Informatics, Japan

CONTACT

M. Walter walterm@in.tum.de