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Call for Papers
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2017 IEEE International Conference on Computer Design (ICCD)
Nov 5-8, 2017
Boston Area, Massachusetts USA
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IMPORTANT DATES:
June 16 Abstract submission
June 23 Full paper submission
Sep 1 Notification of Acceptance
Sep 29 Final paper
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Webpage: http://www.iccd-conf.com

The International Conference on Computer Design (ICCD) encompasses a wide range of topics in the research, design, and implementation of computer systems and their components. ICCD's multi-disciplinary emphasis provides an ideal environment for developers and researchers to discuss practical and theoretical work covering system and computer architecture, test, verification and security, design and technology, and tools and methodologies. Manuscripts describing original work on any topic from the scope of ICCD are welcome. Authors are asked to submit technical papers in accordance to the author's instructions in one of the following five conference tracks (see also the track details at the bottom):

* Computer Systems and Applications
* Processor Architecture
* Logic and Circuit Design
* Electronic Design Automation
* Test, Verification, and Security

The full version of the paper should be a PDF file following the submission guidelines that will be made available at the conference website. Submission issues should be directed to the program chairs at os22@nyu.edu and uogras@asu.edu. See the ICCD 2017 website at http://www.iccd-conf.com for additional information about the conference and submission details.

The highest-ranking papers of ICCD 2017 will be invited for inclusion in the IEEE Transactions on Emerging Technologies in Computing (TETC) Special Issue. If the authors accept the invitation, the paper will be assumed to have gone through one round of revisions. Publication in the IEEE TETC Special Issue will replace publication in the ICCD Proceedings.

With generous support from the U.S. National Science Foundation, ICCD 2017 will offer travel grants for students to defray a portion of their travel cost. The size and number of these grants will vary depending on funding availability, the number of student applicants, and their respective priority. Grant awards will be made before the early registration deadline, and more information about applying for this grant will be posted on the ICCD webpage.


General Chairs: Omer Khan (UCONN) and Sule Ozev (ASU)
Program Chairs: Ozgur Sinanoglu (NYUAD) and Umit Ogras (ASU)

Sponsored by the IEEE Computer Society TC on Computer Architecture, IEEE Circuits and Systems Society, and the U.S. National Science Foundation




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TRACK DETAILS:

Computer Systems and Applications: Advanced computer architecture for general and application-specific enhancement; Software design for embedded, mobile, general-purpose, cloud, and high-performance platforms; IP and platform-based designs; HW/SW codesign; Modeling and performance analysis; Support for security, languages and operating systems; Hardware/software techniques for embedded systems; Application-specific and embedded software optimization; Compiler support for multi-threaded and multi-core designs; Memory system and network system optimization; On-chip and system-area networks; Support for communication and synchronization.

Processor Architecture: Microarchitecture design techniques for uni- and multi-core processors: instruction-level parallelism, pipelining, caching, branch prediction, multithreading; Techniques for low-power, secure, and reliable processors; Embedded, network, graphic, system-on-chip, application specific and digital signal processor design; Hardware support for processor virtualization; Real-life design challenges: case studies, tradeoffs, postmortems.

Logic and Circuit Design: Circuits and design techniques for digital, memory, analog and mixed-signal systems; Circuits and design techniques for high performance and low power; Circuits and design techniques for robustness under process variability and radiation; Design techniques for emerging process technologies (MEMs, spintronics nano, quantum, flexible electronics); Asynchronous circuits; Signal processing, graphic processor and arithmetic circuits.

Electronic Design Automation: High-level, logic and physical synthesis; Physical planning, design and early estimation for large circuits; Automatic analysis and optimization of timing, power and noise; Tools for multiple-clock domains, asynchronous and mixed timing methodologies; CAD support for FPGAs, ASSPs, structured ASICs, platform-based design and NOC; DfM and OPC methodologies; System-level design and synthesis; Tools and design methods for emerging technologies (MEMs, spintronics, nano, quantum).

Test, Verification and Security: Design error debug and diagnosis; Fault modeling; Fault simulation and ATPG; Analog/RF Testing; Statistical Test Methods; Large volume yield Analysis and Learning; Fault tolerance; DFT and BIST; Functional, transaction-level, RTL, and gate-level modeling and verification of hardware designs; Equivalence checking, property checking, and theorem proving; Constrained-random test generation; High-level design and SoC validation. Hardware security primitives; Side channel analysis; Logic and microarchitectural countermeasures; Hardware security for IoT; Interaction between VLSI test and trust.